Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments

TLDR

Nano‑scale CMOS latches are increasingly vulnerable to radiation‑induced multiple‑node upset errors. The paper proposes the QNUTL latch, which fully tolerates up to quadruple‑node upsets, and a power‑efficient QNUTL‑CG variant. QNUTL is built from three dual‑interlocked storage cells and a triple‑level soft‑error interceptive module of six 2‑input C‑elements, while QNUTL‑CG replaces the DICEs with clock‑gating cells to reduce power. Simulations confirm full MNU tolerance and demonstrate that QNUTL‑CG achieves lower area, delay, and setup time than the state‑of‑the‑art TNUTL.

Abstract

With the rapid advancement of CMOS technologies, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations. First, this paper proposes a novel latch design, namely QNUTL that can completely tolerate MNUs such as double-node upsets, triple-node upsets (TNUs), and even quadruple-node upsets (QNUs). The latch is mainly constructed from three dual-interlocked-storage-cells (DICEs) and a triple-level soft-error interceptive module (SIM) that consists of six 2-input C-elements. Due to the single-node-upset self-recoverability of DICEs and the soft-error interception of the SIM, the latch can completely tolerate any QNU. Next, by replacing the DICEs in the QNUTL latch by clock-gating (CG) based ones, a QNUTL-CG latch is proposed to significantly reduce power consumption. Simulation results demonstrate the MNU-tolerance of the proposed latches. Moreover, owing to the use of a high-speed transmission path, clock-gating, and a few transistors, the proposed QNUTL-CG latch has low overhead in terms of area, D-Q delay, CLK-Q delay, and setup time, compared with the state-of-the-art TNU-tolerant latch (TNUTL) which is not QNU-tolerant.