Doping of n+ and p+ polysilicon in a dual-gate CMOS process - Concepedia

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Doping of n+ and p+ polysilicon in a dual-gate CMOS process

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References

1988

Year

C. Y. Wong, J.Y.-C. Sun, Yuan Taur, C. S. Oh, R. Angelucci, B. Davari

International Electron Devices Meeting

Electrical EngineeringEngineeringPhysicsNanoelectronicsBias Temperature InstabilityApplied PhysicsDual-gate Cmos ProcessSemiconductor Device FabricationSilicon On InsulatorMicroelectronicsP+ PolysiliconSemiconductor Device

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