Processing-In-Memory-Based On-Chip Learning With Spike-Time-Dependent Plasticity in 65-nm CMOS

Abstract

A processing-in-memory (PIM)-based accelerator is presented in 65-nm CMOS for on-chip learning in spiking neural network using timing-based stochastic spike-timing-dependent plasticity (STDP). The design uses mixed-signal processing in the 8T-SRAM array for spike accumulation and all-digital computation for neuron dynamics and synaptic weight updates. The 0.39-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 14.83-mW test chip demonstrates 100K images/second learning rate and 148.3 nJ/image learning energy.