Correction of Delay-Time-Induced Maximum Junction Temperature Offset During Electrothermal Characterization of IGBT Devices

Abstract

The lifetime evaluation is strongly influenced by the measurement accuracy of the junction temperature with the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ce</sub> (T) method during power cycling test (PCT). However, the measurement delay time tmd, the time between which the load current is switched off and the test pulse is applied, induces a maximum junction-temperature offset ΔT <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">jm</sub> . The JEDEC [1] suggested square root t method is found only to be suitable for devices with surface-close heat generation and will induce errors for other devices such as IGBTs. In this article, two novel methods, the simulated ΔZ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> and the Cauer thermal model, are proposed. The principle and accuracy of these two methods are discussed in detail. Furthermore, the measured Z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> curve, or the Foster thermal model method, is proven not suitable for the correction of the maximum junction-temperature offset, as it will induce the same error as the square root t method.