2020 · 16 citations · 20 references
EngineeringComputer EngineeringComputer ScienceDesign AutomationDesign OptimizationField-programmable Gate ArraysAccelerator ArchitectureDesign SynthesisHardware AccelerationHigh-level SynthesisPower OptimizationReconfigurable AcceleratorsAcceleratorsAutomated Design Space ExplorationAutomated Design SynthesisField-programmable Gate Array AcceleratorsField-programmable Gate Arrays (Fpgas)Hardware GenerationReconfigurable Accelerator DesignStatistical Learning Theory
Accelerator design is costly because it requires deep algorithm understanding and extensive optimization, so architects use high‑level synthesis and reconfigurable fabrics to cut expenses. The study aims to further reduce design effort by applying statistical learning. Prospector is an automated framework that employs Bayesian optimization of synthesis directives to lower execution latency and resource consumption on FPGAs. Prospector’s designs approach Pareto efficiency more closely than previous methods, demonstrating improved performance.
Accelerator design is expensive due to the effort required to understand an algorithm and optimize the design. Architects have embraced two technologies to reduce costs. High-level synthesis automatically generates hardware from code. Reconfigurable fabrics instantiate accelerators while avoiding fabrication costs for custom circuits. We further reduce design effort with statistical learning. We build an automated framework, called Prospector, that uses Bayesian techniques to optimize synthesis directives, reducing execution latency and resource usage in field-programmable gate arrays. We show in a certain amount of time designs discovered by Prospector are closer to Pareto-efficient designs compared to prior approaches.
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