Design of High Robustness BNN Inference Accelerator Based on Binary Memristors

Abstract

In-memory computing based on memristor is a promising solution to accelerate on-chip deep neural networks. Concerning the nonideal factors of the device analog behaviors, binary neural network (BNN) with ±1 weight and 0/+1 neuron is an alternative route to better employ the binary memristors with high technical maturity. In this article, we demonstrate a select column scheme for the BNN inference accelerator. By incorporating the performance of a W/AlOx/Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /Pt memristor, the BNN shows high robustness and achieves a high recognition accuracy of 98.31% on the MNIST data set. We further propose a bit error model to investigate the impact of device error on recognition accuracy. The effects of device variation and nonideal input are also considered. The results show that the accuracy keeps satisfying (more than 90%) even under a high invalid rate, high input swing (0.21 standard deviation), and 7% salt noise in binary input, respectively, whereas the device variation has a trivial effect on the network.