A Programmable Frequency Divider With a Full Modulus Range and 50% Output Duty Cycle

Abstract

Programmable frequency dividers with wide modulus range and 50% output duty cycle are highly desirable in the design of frequency synthesizers and phase-locked loops. However, most of the conventional dividers cannot simultaneously achieve a 50% output duty cycle and full modulus range. A programmable frequency divider with a full modulus range, 50% output duty cycle and low phase noise is presented in this paper. To achieve a 50% output duty cycle, the divider employs a novel programmable down-counter based on a modified D flip-flop with a load function. The divider, which was fabricated in a standard 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process, achieves a full 1 to 256 modulus range, 50% output duty cycle, and can operate up to 2.3 GHz with a 1.8-V supply voltage and a power consumption of 3.4 mW. The measured phase noise is −141 dBc/Hz at the frequency offset of 1 MHz when the divider is working at a 1-GHz operational frequency and a division ratio of 10.