Self-Heating and Electrothermal Properties of Advanced Sub-5-nm Node Nanoplate FET

Abstract

In this paper, Self-Heating Effect (SHE) of Gate-All-Around (GAA) nanoplate field effect transistor (FET) with variations of active area specifications including number of vertically stacked channels, metal gate thickness, and channel width, is investigated using TCAD simulations. Our research suggests that varying these architecture parameters not only affect overall performance of sub-5-nm node GAA nanoplate FET such as on-current degradation and time-delay, but also greatly impact thermal reliability such as lattice temperature and thermal resistance, which are comprehensively analyzed using the Figure of Merit (FoM). Furthermore, thermal reliability of GAA nanoplate-FET is analyzed from perspective of Hot Carrier Injection (HCI)/Bias Temperature Instability (BTI) lifetime variation using maximum lattice temperature (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L,max</sub> ) and metal gate thickness (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> ).