Publication | Closed Access
13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique
48
Citations
6
References
2020
Year
Unknown Venue
Non-volatile MemoryEngineeringMemory DesignComputer ArchitectureNand Flash MemoryComputer Memory3D Memory96-Stacked-wl 3DMemory DeviceMemory DevicesParallel ComputingElectrical EngineeringFlash MemorySynchronous DesignComputer EngineeringComputer ScienceMicroelectronicsSolid State DrivesMemory ReliabilityMemory ArchitectureStorage AssignmentProgram TimeSemiconductor MemoryIn-storage Computing
Ever since a 3b/cell (TLC) NAND Flash memory became the mainstream in nonvolatile memory market, a new demand for a 4b/cell (QLC) NAND flash memory has been emerging for low-cost applications. However, QLC has inherently much longer page program time than TLC because of 16-state programming within a limited program and erase (PE) window, as well as narrower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> distributions. The longer page-program time, subsequently, degrades sequential write performance. Thus it is not possible to meet the required sequential-write performance in applications such as mobile devices and solid state drives (SSDs).
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