Publication | Closed Access
Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its Applications
162
Citations
13
References
2020
Year
Unknown Venue
Mathematical ProgrammingCluster ComputingCombinatorial Optimization ProblemsEngineeringAdvanced ComputingComputer ArchitectureComputational ComplexitySupercomputer ArchitectureDiscrete OptimizationDigital AnnealerOperations ResearchSimulated AnnealingHigh-performance ArchitectureIsing ModelSystems EngineeringParallel ComputingCombinatorial OptimizationMassively-parallel ComputingHigh-speed SolvingCombinatorial ProblemComputer EngineeringComputer ScienceEdge ComputingOptimization ProblemParallel ProgrammingDedicated Architecture
A Digital Annealer (DA) is a dedicated architecture for high-speed solving of combinatorial optimization problems mapped to an Ising model. With fully coupled bit connectivity and high coupling resolution as a major feature, it can be used to express a wide variety of combinatorial optimization problems. The DA uses Markov Chain Monte Carlo as a basic search mechanism, accelerated by the hardware implementation of multiple speed-enhancement techniques such as parallel search, escape from a local solution, and replica exchange. It is currently being offered as a cloud service using a second-generation chip operating on a scale of 8,192 bits. This paper presents an overview of the DA, its performance against benchmarks, and application examples.
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