Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells

Abstract

We present a side-channel-attack (SCA) resistant Advanced Encryption Standard (AES) accelerator by means of asynchronous-logic (async) based on the standard library cells. To mitigate SCA, we adopt the dual-rail logic, and propose a delayed completion tree (to introduce delay variations) and the data flow control (to halt reset operation at the last round). We further perform a comprehensive SCA evaluation (with 7 attacking/power models) by means of power simulations. To the best of our knowledge, such comprehensive SCA evaluation has never been reported for other async AES or its sub-block designs. Based on the basis of 5k power simulations, we show that our proposed async AES accelerator are unbreakable. Our proposed async AES accelerator occupies 420μm×420μm @ 65nm CMOS and dissipates 2nJ/encryption @ 1.2V.