2019 · 59 citations · 13 references
EngineeringComputer EngineeringComputer ScienceDesign AutomationDesign ComputationVlsi DesignDesign Rule CheckingPhysical DesignRoutingRouting AlgorithmsRouting ArchitectureVery-large-scale Integration LayoutComplexityDetailed RoutingPinsScalable RoutingScalable Routing ArchitecturesVery-large-scale Integration (Vlsi) DesignVlsi ImplementationWirelength Optimization
Detailed routing becomes a crucial challenge in VLSI design with shrinking feature size and increasing design complexity. More complicated design rules were added to guarantee manufacturability, which made detailed routing an even harder task to achieve in the design flow. In this paper, we propose a detailed router that judiciously handles hard-to-access pins and new design rules including length-dependent parallel run length spacing, end-of-line spacing with parallel edges, and corner-to-corner spacing. Our experimental results show that our framework can effectively reduce the number of violations with comparable wirelength. Comparing our algorithm with the best score of each released designs in the ISPD'19 Contest, there is 2% score improvement. Compared with the state-of-the-art work, our algorithm achieves 69% better scores. The source code of Dr. CU 2.0 is available at https://github.com/cuhk-eda/dr-cu.
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ISPD 2018 Initial Detailed Routing Contest and Benchmarks
Stefanus Mantik, Gracieli Posser, Wing-Kai Chow et al. · 2018 · 69 citations