A 10-b 320-MS/s Dual-Residue Pipelined SAR ADC with Binary Search Current Interpolator

Abstract

This paper presents a 10-bit 320-MS/s dual-residue pipelined SAR ADC. In the proposed ADC, an open-loop gain stage is employed without any calibration by relaxing the offset, gain, and linearity requirements of the inter-stage residue amplifier. Also, a binary search current interpolation is proposed for further quantization of the two residue signals. With a gm-cell residue amplifier and two 5-bit current interpolators, the second stage SAR operation is performed using a single comparator. The prototype ADC is fabricated in a 28 nm CMOS process with an active die area of 0.015 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Operating at a sampling rate of 320 MHz, the ADC achieves a SNDR and a SFDR of 54.0 dB and 66.4 dB, respectively, at the Nyquist input frequency. It consumes 5.45 mW at a 1.0 V supply voltage, resulting in a Nyquist FoM of 41.6 fJ/conversion-step.