Impact of Thermal Boundary Resistance on the Performance and Scaling of Phase-Change Memory Device

Abstract

The scaling of RESET current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RESET</sub> ) used for reamorphization in phase-change memory (PCM) devices has been a challenging task to meet the energy-efficient programming. The faithful prediction of IRESET of scaled-down devices demands realistic physical models in order to examine lowpower, miniaturized device characteristics, and the potential of a highly scalable PCM technology. Therefore, modeling the intrinsic interface effects, thermal boundary resistance (TBR) at the GeSbTe (GST)-metal and GST-oxide interfaces, and electrical interface resistance (EIR) at the GST-metal interface of the nanoscale PCM device is necessary. In this paper, the impact of presence and absence of TBR and EIR on IRESET in a mushroomtype PCM device is investigated, and their usefulness on scaling is predicted for diminished devices. Reductions in IRESET, 32% in the case of 100 nm contact diameter (CD), 45% for the 40-nm CD and 73% for the 10-nm CD are achieved by taking into account of interface effects, and these results are validated with experimental results published elsewhere. The fitted model suggests I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RESET</sub> scales down linearly with CD and necessitates for the combined effects of TBR and EIR to successfully follow the isotropic scaling in mushroom-type devices. Hence, our simulation results demonstrate the significance of TBR and EIR for a better optimization and a reliable prediction of IRESET for low-power programming of PCM devices toward enabling next generation high-speed, high-density nonvolatile memory applications.