A novel 4H-SiC trench MOSFET with double shielding structures and ultralow gate-drain charge

Abstract

Abstract A new ultralow gate–drain charge ( Q GD ) 4H-SiC trench MOSFET is presented and its mechanism is investigated by simulation. The novel MOSFET features double shielding structures (DS-MOS): one is the grounded split gate (SG), the other is the P + shielding region (PSR). Both the SG and the PSR reduce the coupling effect between the gate and the drain, and transform the most part of the gate–drain capacitance ( C GD ) into the gate–source capacitance ( C GS ) and drain–source capacitance ( C DS ) in series. Thus the C GD is reduced and the proposed DS-MOS obtains ultralow Q GD . Compared with the double-trench MOSFET (DT-MOS) and the conventional trench MOSFET (CT-MOS), the proposed DS-MOS decreases the Q GD by 85% and 81%, respectively. Moreover, the figure of merit (FOM), defined as the product of specific on-resistance ( R on, sp ) and Q GD ( R on, sp Q GD ), is reduced by 84% and 81%, respectively.