REACT: Read/Write Error Rate Aware Coding Technique for Emerging STT-MRAM Caches

Abstract

Spin-transfer torque magnetic RAMs (STT-MRAMs) are the most promising alternative for static random-access memories in large last-level on-chip caches due to their higher density and near-zero leakage power. However, the reliability of STT-MRAMs is threatened by high probability of read disturbance and write failure. Both read disturbance and write failure, which cause a soft error in the cache cells, have an asymmetric behavior. Read disturbance occurs only in STT-MRAM cells storing “1” value, and write failure error rate in a 0 → 1 transition is much higher than that in a 1 → 0 transition. In this paper, we propose Read/write Error-rate Aware Coding Technique (REACT) to improve the reliability of the emerging STT-MRAM caches. REACT decreases the read disturbance and write failure rates by reducing the total number of “1”s and 0 → 1 transitions on a cache block update. Our simulation results show that REACT reduces the probability of read disturbance and write failure up to 58% and 71%, respectively. These improvements are achieved by imposing negligible area, power, and performance overheads (less than 1%).