A 25ns 1Mb CMOS SRAM

Abstract

HIGH-SPEED OPERATION and low-power consumption are crucial requirements for the new generation high density SR.4kIs. This paper will describe development of a Mb chip with a typical address access time of 25ns and typical operating current of 15mA. Desired performance has been realized by bit-line circuitry (LOAF bit line), a 2-stage sense amplifier utilizing renewed double word-line structure, address transition detection techniques and a 0.8μm CMOS process with double-level polysilicon and double-level aluminum layers