Design-Technology Co-Optimization of Standard Cell Libraries on Intel 10nm Process

Abstract

This paper highlights the co-optimization of process technology, std. cell library offerings and block-level TFM on Intel 10nm node to enable unprecedented scaling opportunity for products ranging from high performance client/server to low power mobile/IoT segments. The 10nm short height library enables 2.7x transistor density scaling going from 14nm counterpart. The taller height libraries are optimized to meet performance and reliability requirements of Intel's leading edge client/server products. PPA trade-offs are analyzed both at std. cell level and block level on an industry standard Core IP design.