A 1.1-pJ/cycle, 20-MHz, 0.42-V Temperature Compensated ARM Cortex-M0+ SoC With Adaptive Self Body-Biasing in FD-SOI

Abstract

This letter introduces the first ultra-low-voltage ARM Cortex-M0+ system-on-chip leveraging fully depleted silicon-on-insulator technology through adaptive self body biasing swapping techniques for optimum power consumption over a 0 °C-60 °C temperature range. A power management unit enables Active and Sleep modes as well as a power-free body bias swapping depending on the core's modes and temperature. The system minimum energy point, implemented in a 22-nm node, is reported at 0.42 V/20 MHz, with a 1.13-pJ/cycle energyefficiency. A temperature compensation scheme is also implemented. When the temperature drops the system is placed in a forward body biasing mode, providing an additional energy boost and maintaining the operating frequency. Over 22.5 °C the self body biasing techniques allow to swap the n-well and p-well connections to reduce the transistor leakage by 27%, leading to 28.3-μW Active power and 2.78 μW in DeepSleep mode.