An Asynchronous Energy-Efficient CNN Accelerator with Reconfigurable Architecture

Abstract

In this paper, we introduce an asynchronous energy-efficient convolutional neural network (CNN) accelerator with reconfigurable architecture including six computing cores, each of which contains 5x5 processing elements. With the dynamically reconfigurable architecture, the data path, the calculation method, the activation function, and the pooling way and size can be modified according to the configurable information for different CNN models. In the computing cores, the global clock is replaced by the local pulse signals from Click elements. An asynchronous pipeline formed by Click elements enables the circuits to work in pipeline mode without any sacrifice of speed because of the self-timed characteristic of asynchronous circuits. Each computing core has a 5x5 registers array that is fully connected by an asynchronous Mesh network, by which the input data can be fully reused. A novel computing pattern called convolution-and-pooling-integrated computing, which combines convolution and pooling computing together, is proposed to reduce the access to the intermediate data. These yield an 88% decrease of the access to off-chip memory, which significantly reduces energy consumption. A CNN model, LeNet-5, is implemented in our accelerator with the FPGA of Xilinx VC707. The asynchronous computing core has 84% less dynamic power than that of the synchronous core. The efficiency achieves 30.03 GOPS/W, which is 2.1 times better than that of previous works.