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Bitline Charge-Recycling SRAM Write Assist Circuitry for <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm{MIN}}$ </tex-math> </inline-formula> Improvement and Energy Saving
16
Citations
21
References
2018
Year
EngineeringVlsi DesignMemory DesignEnergy EfficiencyEmerging Memory TechnologyComputer ArchitectureComputer MemoryHorizontal Cvss RoutingMemory DevicesTex-math Notation=Vertical Cvss RoutingElectrical EngineeringElectronic MemoryComputer EngineeringHspice SimulationsEnergy SavingMicroelectronicsMemory ReliabilityMemory ArchitectureLow-power ElectronicsCircuit DesignSemiconductor MemoryResistive Random-access Memory
Bitline (BL) charge-recycling-based static random access memory (SRAM) write assist circuits (BCR-WA) are proposed to reduce the minimum operating voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> ) of SRAM. In the proposed schemes, the charges stored on the unselected BL are utilized to raise the cell ground voltage (VSS) of the selected bit cell, and the increased cell VSS (CVSS) enhances the write ability. According to the metal routing direction of CVSS in the layout, two types of BCR-WA are proposed, BCR-WA for vertical CVSS routing (BCR-WA <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</sub> ) and horizontal CVSS routing (BCR-WA <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</sub> ). To evaluate the proposed circuits, HSPICE simulations are performed and the test chip is implemented using a 14-nm FinFET technology. Thanks to the charge-recycling operation, BCR-WA <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</sub> and BCR-WA <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</sub> can save energy by 11%-44% and 30%-66%, respectively, compared to the previous write assist circuits, with a comparable or less area overhead and an insignificant degradation in read performance (<;1%) and stability (~25-mV degradation in maximum word-lin voltage). In addition, according to simulation results, BCR-WA <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</sub> and BCR-WA <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</sub> can lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> by 150 mV. In particular, silicon measurement result for BCR-WAH proves an 125-mV improvement in V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> .
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