An Ultra-Dense 2FeFET TCAM Design Based on a Multi-Domain FeFET Model

TLDR

TCAMs are widely used in routers, caches, and machine learning, and researchers are exploring non‑volatile technologies such as FeFETs for improved energy and delay; FeFETs offer high ION/IOFF, efficient voltage‑driven write, low cost, and CMOS compatibility. The study proposes a 2FeFET TCAM design based on a state‑of‑the‑art, experimentally calibrated FeFET model. The design employs a state‑of‑the‑art, experimentally calibrated FeFET model. The 2FeFET TCAM achieves 3.5× lower write energy and 4.1× lower search energy‑delay product than CMOS TCAMs, while its cell area is 13% of CMOS and comparable to ReRAM designs.

Abstract

Ternary content addressable memories (TCAMs) represent a form of logic-in-memory and are currently widely used in routers, caches, and efficient machine learning models. From a technology prospective, researchers have begun to consider various non-volatile (NV) memory technologies to design NV TCAMs that may offer improvements with respect to figures of merit, such as energy and delay when compared to conventional CMOS designs. Among these devices, ferroelectric field effect transistors (FeFETs) stand out due to their high ION/IOFF ratio, efficient voltage-driven write mechanism, low-cost, and CMOS-compatible fabrication process. We propose a 2FeFET TCAM design based on a state-of-the-art, experimentally calibrated FeFET model. We evaluate and compare our design with other TCAMs at the cell and array levels. Our results suggest that a 2FeFET TCAM requires 3.5×/3200× less write energy than CMOS/resistive random access memory (ReRAM) TCAMs, respectively. The cell area is 13% of that of a CMOS TCAM, and is on par with ReRAM designs. The search energy-delay-product of a 2FeFET TCAM is also 4.1×/2.8× less than CMOS/ReRAM TCAMs, respectively.