The influence of grain boundary interface traps on electrical characteristics of top select gate transistor in 3D NAND flash memory

Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

Hidetake Tanaka, M. Kido, K. Yahashi et al. · 2007 · 585 citations

Engineering, Computer Engineering, Electrical Engineering +16

Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation

I‐Wen Wu, T.Y. Huang, W. B. Jackson et al. · IEEE Electron Device Letters · 1991 · 244 citations

Engineering, Electrical Engineering, Materials Science +17

Effects of trap-state density reduction by plasma hydrogenation in low-temperature polysilicon TFT

I‐Wen Wu, A.G. Lewis, T.Y. Huang et al. · IEEE Electron Device Letters · 1989 · 112 citations

Engineering, Electrical Engineering, Physics +16

2019 Symposium on VLSI Technology Digest of Technical Papers

2019 · 95 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +14

Evaluation of grain boundary trap states in polycrystalline–silicon thin-film transistors by mobility and capacitance measurements

Hiroyuki Ikeda · Journal of Applied Physics · 2002 · 72 citations

Engineering, Electrical Engineering, Materials Science +17