Publication | Open Access
Sputter-Deposited-MoS<sub>2</sub>${n}$ MISFETs With Top-Gate and Al<sub>2</sub>O<sub>3</sub>Passivation Under Low Thermal Budget for Large Area Integration
13
Citations
47
References
2018
Year
SemiconductorsLarge AreaElectrical EngineeringProcess EnduranceEngineeringSemiconductor TechnologyNanoelectronicsApplied PhysicsLow Thermal BudgetSemiconductor Device FabricationLarge Area IntegrationMicroelectronicsSemiconductor DevicePassivation Films
We have fabricated large area integrated top-gate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> MISFETs with sputter-deposited-MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> film having n-type operation. A sputtering method enables us to form a large-area MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> thin film followed by H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> S annealing to compensate sulfur vacancies. Two passivation films of ALD-Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> enhance the process endurance of MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> channel. Therefore, we demonstrate TiN-top-gate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> MISFET, which is a substantial first step to realize industrial chip-level LSIs with MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -channel FETs.
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