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High Endurance Self-Heating OTS-PCM Pillar Cell for 3D Stackable Memory
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2018
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Materials ScienceNon-volatile MemoryElectrical EngineeringEngineeringEmerging Memory TechnologyApplied PhysicsPillar DeviceComputer ArchitectureHigh Endurance OtsMemory DeviceSemiconductor MemoryIntegrated CircuitsStackable MemoryElectronic PackagingMicroelectronicsPhase Change MemoryProgram Endurance
For the first time published, high endurance OTS (ovonic threshold switch, here, TeAsGeSiSe-based) is integrated with PCM (here, doped Ge2Sb2Te5) to form a 3D stackable pillar type device. With the help of an etch buffer layer and a damage-free pillar RIE process, we achieved 100% array yield without OTS/PCM composition modification. Anneal tests show this one-selector/one-resistor (1S1R) pillar device is BEOL-compatible.We report excellent electrical performance by 1S1R OTS-PCM device; selector provides the fast turn on/off speed which enables 10ns fast RESET speed, program endurance is 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> cycles, and read endurance is higher than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cycles.