Match-Line Division and Control to Reduce Power Dissipation in Content Addressable Memory

Abstract

Hardware search engines are widely used in network routers for high-speed look up and parallel data processing. Content addressable memory (CAM) is such an engine that performs high-speed search at the expense of large energy dissipation. Match-line (ML) power dissipation is one of the critical concerns in designing low-power CAM architectures. NOR-MLs make this issue more severe due to the higher number of shortcircuit discharge paths during search. In this paper, an ML control scheme is presented that enables dynamic evaluation of a match-line by effectively activating or deactivating ML sections to improve the energy efficiency. 128×32-bit memory arrays have been designed using 45-nm CMOS technology and verified at different process-voltage-temperature and frequency variations to test the improvements of performance. A search frequency of 100 MHz under 1-V supply, at 27 °C applied on the proposed CAM results 48.25%, 52.55%, and 54.80% reduction in energy per search compared to a conventional CAM, an early predict and terminate ML precharge CAM (EPTP-CAM) and an ML selective charging scheme CAM, respectively. ML partition also minimizes precharge activities between subsequent searches to reduce total precharge power in the proposed scheme. An approximate reduction of 2.5 times from conventional and EPTP schemes is observed in the precharge dissipation. Besides low search power, proposed design improves the energy-delay by 42% to 88% from compared designs.