Anup Dandapat - Concepedia

Author

Anup Dandapat

National Institute of Technology Meghalaya ORCID

Also Known As

A Dandapat, A K Dandapat, A. Dandapat, ANUP DANDAPAT, Anup Dandapat

Publications

973

Citations

H-Index

Concepts

All Affiliations

National Institute of Technology Meghalaya Indian Institute of Engineering Science and Technology, Shibpur Jadavpur University University of Kalyani Indian Institute of Information Technology, Pune

About

Anup Dandapat is an author at National Institute of Technology Meghalaya specializing in engineering, computer engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	12	12	577
2	Computer Engineering	11	11	564
3	Electrical Engineering	9	9	468
4	Computer Science	6	6	181
5	Systems Engineering	1	1	17

Anup Dandapat

Publications

817

Citations

H-Index

Page 1

	Year	Citations
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit Partha Bhattacharyya, Bijoy Kundu, Sovan Ghosh, IEEE Transactions on Very Large Scale Integration (VLSI) Systems Low-power ElectronicsElectrical EngineeringFull Adder DesignsVlsi DesignPerformance Analysis	2014	307
High speed ASIC design of complex multiplier using Vedic Mathematics Prabir Saha, Abhijit Banerjee, Partha Bhattacharyya,	2011	87
ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics Prabir Saha, Arindam Banerjee, Anup Dandapat, Microelectronics Journal	2011	50
Self-Controlled High-Performance Precharge-Free Content-Addressable Memory Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat IEEE Transactions on Very Large Scale Integration (VLSI) Systems Hardware SecurityMl DelayNon-volatile MemoryEngineeringHigh-performance Architecture	2017	48
Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Sandeep Mishra, IEEE Transactions on Circuits and Systems I Regular Papers Non-volatile MemoryEngineeringMemory DesignEmerging Memory TechnologyComputer Architecture	2020	44
A 1.2-Ns16×16-Bit Binary Multiplier Using High Speed Compressors Anup Dandapat, Sandip Ghosal, Partha Sarkar, Zenodo (CERN European Organization for Nuclear Research)	2010	33
A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications Sandeep Mishra, Telajala Venkata Mahendra, Anup Dandapat IEEE Transactions on Circuits and Systems I Regular Papers Non-volatile MemoryEngineeringVlsi DesignComputer ArchitectureMask Storage	2016	31
Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique D. Kayal, Posiba Mostafa, Anup Dandapat, Journal of Signal Processing Systems Electrical EngineeringEngineeringComputer EngineeringVedic Multiplication AlgorithmBit Multiplier	2013	28
Match-Line Division and Control to Reduce Power Dissipation in Content Addressable Memory Sheikh Wasmir Hussain, Telajala Venkata Mahendra, Sandeep Mishra, IEEE Transactions on Consumer Electronics Non-volatile MemoryEngineeringVlsi DesignComputer ArchitecturePower Optimization	2018	28
Improved matrix multiplier design for high‐speed digital signal processing applications Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, IET Circuits Devices & Systems	2014	25

Page 1