Routable and Matched Layout Styles for Analog Module Generation

Abstract

Two 1 novel automatic generation methods for analog layout—a symmetrical twin-row method for MOS transistors and a twisted common-centroid method for capacitor arrays—are introduced. Based on the proposed layout styles and the corresponding algorithms, the symmetry and common-centroid placement patterns for analog devices are realized to guarantee matching properties. On this basis, as the most prominent contribution of this article, channel routing-based algorithms for the proposed layout styles are presented and could achieve 100% routability due to well-arranged devices and corresponding low routing complexity. The algorithms benefits include a small layout area that maximizes the diffusion-sharing of MOS transistors and less routing layer usage for common-centroid device arrays. Moreover, we successfully applied our algorithms to the layout designs of two typical analog modules including a two-stage operating amplifier and a Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). The generated layouts and the circuit simulation results demonstrate the effectiveness of our algorithms in terms of their routability and matching properties. Our algorithms can also be extended to apply to a variety of essential MOS analog circuits.