Concepedia

ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration

Yun Long, Taesik Na, Saibal Mukhopadhyay

IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2018 · 120 citations · 49 references

TL;DR

The authors propose a ReRAM‑based processing‑in‑memory accelerator tailored for recurrent neural networks, differing from earlier CNN‑focused designs. They characterize throughput and energy efficiency through detailed circuit and device simulations, incorporating reprogrammability and an RNN‑friendly pipeline to boost performance. The accelerator delivers a 79× efficiency gain over a GPU baseline, with simulations showing that maintaining read‑noise SD below 0.2, device resistance above 1 MΩ, and minimal write latency is essential for high accuracy and efficiency.

Abstract

We present a recurrent neural network (RNN) accelerator design with resistive random-access memory (ReRAM)-based processing-in-memory (PIM) architecture. Distinguished from prior ReRAM-based convolutional neural network accelerators, we redesign the system to make it suitable for RNN acceleration. We measure the system throughput and energy efficiency with the detailed circuit and device characterization. Reprogrammability is enabled with our design, and an RNN friendly pipeline is employed to increase the system throughput. We observe that on average the proposed system achieves 79× improvement of computing efficiency compared with graphics processing unit baseline. Our simulation also indicates that to maintain high accuracy and computing efficiency, the read noise standard deviation should be less than 0.2, the device resistance should be at least 1 MQ, and the device writes latency should be minimized.