2018 · 22 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignIntegrated Circuit DesignLow-power Digital Circuit DesignVoltage RegulatorsDropout VoltageLow-dropout Regulator DesignLow-dropout RegulatorsLow-power Cmos DesignRecovery TimeTransient DetectionTransient Event DetectionUndershoot
A fully integrated low-dropout regulator (LDO) with ultra-fast transient settling is proposed to provide a clean supply for digital circuits in nano-scale technology. A super source follower (SSF) is inserted into the cascode flipped voltage follower (FVF) topology to drive the power transistor for fast turn-on. The proposed positive transient detection (PTD) circuit drive a NMOS transistor for fast pull-down. The combined effects of these two techniques significantly attenuate the load transient induced voltage spikes. The LDO is designed in a 130 nm CMOS process and consumes 100 μA quiescent current with 1.2 V regulated output and 200 mV dropout voltage. For large load transient of 100 μA to 20 mA and back to 100 μA, the simulated undershoot and overshoot is less than 95 mV with 150 ns recovery time, demonstrating a glitch peak reduction of 6 times and a glitch settling time reduction of 5 times.
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The flipped voltage follower: a useful cell for low-voltage low-power circuit design
R.G. Carvajal, J. Ramı́rez-Angulo, Antonio J. López‐Martín et al. · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 2005 · 692 citations
Engineering, Computer Engineering, Electrical Engineering +17