Integrated CMOS transceivers design towards flexible full duplex (FD) and frequency division duplex (FDD) systems

Abstract

This paper provides an overview of both the challenges and the current state-of-the-art in the areas of full duplex (FD) and frequency division duplex (FDD) integrated transceivers. Implementation hurdles in the form of the linearity, noise, bandwidth (BW) and power of transmitter (TX) self-interference (SI) cancellation circuitry are explored. The difficulty of performing SI cancellation is heavily influenced by the modulation method, the maximum TX power output and the receiver (RX) BW. This paper highlights some recent implementation examples of single-chip FD radios that range in performance from low-power cancellation techniques, to transceivers which target broad channel BW (>40MHz) using high output power transmitters. Several 40nm CMOS devices which range in performance from a narrowband low-energy Bluetooth transceiver to analog-frontends which integrate a +24dBm power amplifier (PA) with a dual-point feedforward cancellation architecture for broadband and deep SI suppression are discussed.