A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS

Abstract

A wide range high resolution 2-stage digital-to-time converter (DTC) is presented. It uses a counter in the first stage and a digitally controlled delay line in the second stage to decouple the range versus resolution trade-off. Background calibration is used to correct interstage gain error. Fabricated in 65nm, the prototype DTC achieves 1.65ps-peak-integral non-linearity (INL) while consuming 10.13mW at 100MHz carrier frequency. The achieved dynamic range is 15dB higher than state-of-the-art DTCs.