A 2.7 pJ/cycle 16 MHz, 0.7 <inline-formula> <tex-math notation="LaTeX">$\mu\text{W}$ </tex-math> </inline-formula> Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI

Abstract

The design of ultra-low-voltage microcontroller (MCU) systems with high energy-efficiency operations is a key concept to achieve fully autonomous energy-harvesting powered Internet-of-Things applications. In this paper, a system-on-chip (SoC) is presented, embedding an ARM <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> Cortex <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> -M0+ MCU, 2×4 KB SRAM, an ultra-low power frequency synthesizer, a custom power switch, and a power management unit enabling the active and sleep modes. The 28 nm fully depleted silicon-on-insulator (FD-SOI) technology has been used to fabricate the device. The whole system operates at a fixed voltage of 0.5 V, and can switch from active and sleep/deep sleep modes, adjusting its frequency from 16 to 8 MHz or 32 kHz in one cycle upon energy availability. Silicon measurements report an SoC's power consumption of 2.7 pJ/cycle at 16 MHz during active mode, and a total power consumption of 0.7 μW during deep sleep mode. By combining frequency and power modes switching with extra reverse body-biasing, the system power consumption is drastically reduced by 2× and 61× in, respectively, sleep and deep sleep modes.