1.6 Gb/s/pin 4-PAM signaling and circuits for a multi-drop bus

Abstract

A 1.6 Gb/s/pin 4-PAM multi-drop signaling system has been implemented in 0.35-/spl mu/m CMOS. The system uses current-mode single-ended signaling, with three DC references shared across six I/O pins. A high-gain windowed integrating receiver with wide common-mode range was designed in order to improve SNR when operating with the smaller input overdrive of 4-PAM. Voltage and timing margins are measured via shmoos in a two-drop bussed system.