2017 · 13 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsDynamic Power ReductionLow-power Digital Circuit DesignComparator DesignComparatorsEnergy-efficient Digital CircuitsGainHigh-speed Cmos DesignLatch DesignLow-power Latch DesignPower Consumption
A modified dynamic comparator is proposed and compared in this paper. A dynamic comparator consists of a low gain amplifier connected to a latch circuit. The inputs are amplified during the evaluation period and the outputs are latched during the regeneration time. The proposed dynamic comparator is fast and consumes less power. At a clock frequency of 1.25GHz and 100mV ΔVin, the delay is 176.71ps and average power consumption is 119.81μW for a supply voltage of 1.8V. The calculated maximum PDP is 24.53 f. The proposed dynamic comparator is suitable for an efficient low power and high speed Flash ADC. The circuits are simulated in cadence virtuoso spectre with 180nm SCL technology.
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Novel approach to high speed CMOS current comparators
H. Träff · Electronics Letters · 1992 · 309 citations
Engineering, Computer Engineering, Electrical Engineering +17
Clocked comparator for high-speed applications in 65nm technology
Mohamed Abbas, Yasuo Furukawa, Satoshi Komatsu et al. · 2010 · 82 citations
Engineering, Computer Engineering, Electrical Engineering +17