TSV-free FinFET-based Monolithic 3D⁺-IC with computing-in-memory SRAM cell for intelligent IoT devices

Abstract

This paper presents the first monolithic 3D vertical cross-tier computing-in-memory (CIM) SRAM cell fabricated using low cost TSV-free FinFET-based 3D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -IC technology. The 9T 3D CIM SRAM cell is able to compute NAND/AND, OR/NOR and XOR/XNOR operations within a single memory cycle. We fabricated stackable multi-fin single-grained Si FinFET using low thermal-budget CO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> far-infrared laser annealing (FIR-LA) for activation and self-aligned silicide. The proposed device achieved high Ion (320 μA/μm (n-FET) and 275 μA/μm (p-FET)) and high I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> /I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> ). The proposed scheme enables the fabrication of energy and area efficient circuits for cost-aware intelligent IoT devices. For proposed 9T CIM SRAM cell, the monolithic 3D device reduces area overhead by 51%, compared to the 2D version, thanks to the stacking of three additional transistors above the 6T SRAM cell.