Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs

TLDR

The paper introduces a family of FIFOs designed for clock‑domain crossings. The authors employ an interleaved architecture for control and data paths, fully synthesizable with standard libraries, and address a common glitch vulnerability with proposed solutions. The resulting FIFOs achieve over 1 GHz throughput in a 65 nm ASIC, exhibit low‑latency fall‑through times, and mitigate the identified glitch hazard.

Abstract

This paper presents a family of FIFOs for clock-domain crossings. These designs are distinguished by an interleaved architecture for the control and data-paths. This approach eliminates most of the throughput bottlenecks in the FIFO design, allowing operation at well over 1GHz in a 65nm process using a standard ASIC design flow. Furthermore, these designs are low-latency: the fall-through time for an empty FIFO is only a few gate delays greater than the synchronizer latency. Our designs are fully synthesizable using widely available design libraries. Furthermore, we identify a glitch vulnerability that is lurking in many published designs, and describe our solutions to these hazards.