Publication | Open Access
High Rate Copper Filling Within High Aspect Ratio Through Silicon Vias for 3-D Chip Stacking
10
Citations
0
References
2006
Year
Materials Science3D Ic ArchitectureChip-scale PackageEngineeringAdvanced Packaging (Semiconductors)Abstract AlgebraMicrofabricationSurface ScienceApplied Physics3-D Chip StackingSilicon ViasChip AttachmentAbstract Object TheoryElectronic PackagingMicroelectronics3D Printing
Abstract not Available.