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CMOS-embedded STT-MRAM arrays in 2x nm nodes for GP-MCU applications
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2017
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Non-volatile MemoryEngineeringEmerging Memory TechnologyMagnetic ResonanceComputer ArchitectureMulti-channel Memory ArchitectureMagnetismRobust Stt-mram TechnologyMemory DeviceMemory DevicesMb ArrayElectrical EngineeringComputer EngineeringMagnetoresistive Random-access MemoryMicroelectronicsMemory ArchitecturePerpendicular Spin-transfer TorqueCmos-embedded Stt-mram ArraysSpintronicsApplied PhysicsSemiconductor Memory
Perpendicular Spin-Transfer Torque (STT) MRAM is a promising technology in terms of read/write speed, low power consumption and non-volatility, but there has not been a demonstration of high density manufacturability at small geometries. In this paper we present an unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS-embedded 40 Mb array. Key features are full array functionality with low BER (bit error rate), process uniformity and reliability, 10 years data retention at 125C with extended endurance to ∼ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> cycles. All achieved with standard BEOL process temperatures. Data retention post 260°C solder reflow temperature cycle is demonstrated.