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Innovative PCM+OTS device with high sub-threshold non-linearity for non-switching reading operations and higher endurance performance
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2017
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Non-volatile MemoryCross Point DeviceEngineeringEmerging Memory TechnologyComputer ArchitectureHigh Sub-threshold Non-linearityIntegrated CircuitsSelector SwitchingPhase Change MemoryMemory DevicesElectrical EngineeringElectronic MemoryPhase-change Memory CellInnovative Pcm+ots DeviceComputer EngineeringMicroelectronicsLow-power ElectronicsNon-switching Reading OperationsSemiconductor Memory
In this paper we present the engineering of a non-volatile 1S1R memory based on a Phase-Change Memory cell (PCM), consisting in a GeN/Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Sb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Te <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> layer, stacked with a GeSe-based Ovonic Threshold Switching selector device (OTS). We optimize and analyze separately the two devices, and we propose for the first time an innovative reading strategy of the cross point device, enabled by the improved sub-threshold non-linearity of the OTS selector. A new memory concept is presented and demonstrated in which selector switching is performed only for SET and RESET programming operations and reading is operated without switching the OTS selector, strategy that allows to target outstanding endurances.