Low‐latency median filter core for hardware implementation of 5 × 5 median filtering

Abstract

This study presents hardware implementation of 5 × 5 median filter that uses a new low‐latency median filter (LLMF) core in order to find the median of 25 integer values. The proposed LLMF core architecture computes the median of 25 integers in just three clock cycles. The maximum frequency of operation of the proposed median filter architecture is 394 MHz on the Xilinx Zynq FPGA device. The proposed LLMF core provides reduced clock cycle latency compared with the existing state‐of‐the‐art median filter core architectures.