Clock Latency Optimization

Clock Latency Optimization is a methodological framework within clock distribution network design that minimizes the propagation delay between the clock source and sequential elements in a synchronous digital system to ensure temporal alignment and improve overall circuit performance.

Publications

1.3K

Citations

156

Authors

Institutions

Publications per year

2017–2026

Parents

Clock Distribution Networks

Publications

A wide-range delay-locked loop with a fixed latency of one clock cycle

Hsiang-Hui Chang, Jyh‐Woei Lin, Ching‐Yuan Yang et al. · IEEE Journal of Solid-State Circuits · 2002 · 156 citations

Engineering, Computer Engineering, Electrical Engineering +16

A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm

Rong-Jyi Yang, Shen-Iuan Liu · IEEE Journal of Solid-State Circuits · 2007 · 153 citations

Engineering, Computer Engineering, Electrical Engineering +17

The GBT-FPGA core: features and challenges

Manoel Barros Marin, S. Baron, Sebastian S. Feger et al. · Journal of Instrumentation · 2015 · 73 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +17

A 480-MHz RISC microprocessor in a 0.12-μm L/sub eff/ CMOS technology with copper interconnects

C. Akrout, Jörg Bialas, M. Canada et al. · IEEE Journal of Solid-State Circuits · 1998 · 65 citations

Engineering, Computer Engineering, Electrical Engineering +17

FPGA implementation of sound encryption system based on fractional-order chaotic systems

Ahmed J. Abd El-Maksoud, Ayman A. Abd El-Kader, Bahy G. Hassan et al. · Microelectronics Journal · 2019 · 59 citations

Engineering, Computer Engineering, Computer Science +17

1–5 of 38

Authors

156

CH
Chih‐Cheng Hsu
National Taiwan University, Taiwan
3 publications · 65 citations
3
h-index
MP
Mark Po-Hung Lin
National Chung Cheng University, Taiwan
3 publications · 65 citations
3
h-index
YC
Yu-Chuan Chen
National Chung Cheng University, Taiwan
3 publications · 65 citations
3
h-index
HC
Hui‐Chi Chen
National Taiwan University Hospital, Taiwan
2 publications · 38 citations
2
h-index
YL
Yih-Lang Li
National Yang Ming Chiao Tung University, Taiwan
2 publications · 38 citations
2
h-index

1–5 of 156

Institutions

1–8 of 60

Venues

IEEE Journal of Solid-State Circuits
4 publications · 425 citations
4
h-index
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2 publications · 63 citations
2
h-index
International Conference on Computer Aided Design
Conference · 1 publications · 13 citations
1
h-index
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Conference · 1 publications · 15 citations
1
h-index
Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)
Conference · 1 publications · 12 citations
1
h-index

1–5