2017 · 141 citations · 11 references
EngineeringComputer EngineeringComputer ScienceHardware Description LanguagesReconfigurable ComputingSystem-on-chip DesignConfigurable Logic BlocksDynamic ReconfigurationMemory Hierarchy OptimizationProgrammable Logic DevicesReconfigurable System ArchitectureRun-time ReconfigurationPipeline ArchitectureProgrammable Logic DesignReconfigurable Computing ArchitecturesReconfigurable Logic Architecture
We present dRMT (disaggregated Reconfigurable Match-Action Table), a new architecture for programmable switches. dRMT overcomes two important restrictions of RMT, the predominant pipeline-based architecture for programmable switches: (1) table memory is local to an RMT pipeline stage, implying that memory not used by one stage cannot be reclaimed by another, and (2) RMT is hardwired to always sequentially execute matches followed by actions as packets traverse pipeline stages. We show that these restrictions make it difficult to execute programs efficiently on RMT.
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Compiling packet programs to reconfigurable switches
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