2017 · 70 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignElectron Beam LithographyIntegrated Circuit DesignInterconnect TechnologyPhysical DesignVery-large-scale Integration LayoutCmos Fabrication ProcessesFin Field-effect TransistorsGate Stack EngineeringHigh PerformanceHigh-speed Cmos DesignMask Set DesignPerformance Fidelity
7nm CMOS FinFET technology featuring EUV lithography, 4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> gen. dual Fin and 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> gen. multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total power over 10nm technology [1]. EUV lithography, fully applied to MOL contacts and minimum-pitched metal/via interconnects, can reduce >25% mask steps with higher fidelity and smaller CD variation. A <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</inf> of 6T HD SRAM cell are 1.29 for PD (PG) and 1.34 for PU, respectively.