A Threshold Voltage Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects

Abstract

In this paper, the influence of substrate bias voltage and substrate-induced surface potential (SISP) on threshold voltage of tri-gate junctionless field-effect transistors (TG-JLFETs) has been investigated. For this purpose, a quasi-3-D threshold voltage model of TG-JLFETs is presented considering the effects of both back-bias voltage and a lightly doped substrate. To incorporate the effect of SISP on the threshold voltage, the boundary conditions at the silicon-buried oxide interface have been modified accounting for the potential difference between substrate surface and substrate bulk. Model results are compared with the simulation results obtained using 3-D visual TCAD device simulator from Cogenda.