DC Offset Rejection Improvement in Single-Phase SOGI-PLL Algorithms: Methods Review and Experimental Evaluation

Abstract

DC offset in the input of phase-locked loops (PLLs) is a challenging problem since it will result in fundamental frequency oscillations in the estimated phase and frequency. In this paper, a comprehensive analysis and performance evaluation of several advanced second-order generalized integrator (SOGI)based PLL methods in enhancing the dc offset rejection capability for single-phase grid-connected power converters is presented. These methods include the cascade SOGI, modified SOGI, αβ-frame delayed signal cancellation (DSC), complex coefficient filter, in-loop dq-frame DSC, notch filter, and moving average filter-based SOGI-PLL. Main characteristics and design aspects of these methods are presented. Main performance indexes, such as the setting time, frequency or phase errors are defined and these methods are systematically compared under various scenarios with both numerical and experimental results.