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Space-charge-limited current in nanowires
30
Citations
19
References
2017
Year
SemiconductorsElectrical EngineeringSemiconductor DeviceEngineeringPhysicsNanotechnologyNanoelectronicsApplied PhysicsGeometric ScalingNanowire Impurity ConcentrationSemiconductor MaterialSemiconductor NanowiresThin FilmsCharge Carrier TransportMicroelectronicsCharge TransportElectrical PropertyElectrical Insulation
Space-charge-limited current is often observed in semiconductor nanowires due to carrier depletion and reduced electrostatic screening. We present a numerical study on geometric scaling of the space-charge-limited current in nanowires, in comparison with the thin film and bulk geometries, using an n+-n-n+-model. The model highlights the effects of the surroundings for thin films and nanowires and shows that the dielectric properties of the semiconductor have a negligible effect on the space-charge-limited transport for small dimensions. The distribution of equilibrium and injected charge concentration vary as the semiconductor dimensionality is reduced. For low doping, the ohmic current is controlled by charge diffusion from degenerate contacts rather than by the nanowire impurity concentration. The results of numerical calculations agree with a simple capacitance formalism which assumes a uniform charge distribution along the nanowire, and experimental measurements for InAs nanowires confirm these results. The numerical model also predicts that an asymmetric nanowire contact geometry can enhance or limit charge injection.
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