Ultra-Low On-Resistance LDMOS With Multi-Plane Electron Accumulation Layers

Abstract

An ultra-low specific ON-resistance (Ron,sp) LDMOS is proposed and investigated by simulation in this letter. It features an extended tri-gate, a trench source, and a trench drain. in the on-state, multi-plane electron accumulation layers (MALs) and hence multiple ultra-low resistance current paths are formed along the bottom surface and side wall of the extended tri-gate. In the off-state, the extended gate assists in depleting the drift region and thus increases the doping concentration of the drift region (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ). Both contribute to an ultralow ON-resistance. Moreover, the combined structure of the extended gate and tri-gate enhances the transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) of the device. Additionally, the trench source and the trench drain shorten the current paths. As a consequence, both the current under the extended tri-gate and the total current increase. The performance of the MAL LDMOS is superior to that of the current state of art. Compared with the 70 V conventional LDMOS (Con. LDMOS) with the same dimension, the MAL LDMOS reduces the R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> by 90% and doubles the g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> owing to the multi-plane accumulation layers. The MAL LDMOS maintains nearly the same breakdown voltage as the Con. LDMOS.