IEEE Transactions on Device and Materials Reliability · 2017 · 24 citations · 11 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDevice ReliabilityHardware Fault ToleranceMemory DevicesMemory Subsystem DesignCmos ReliabilityComplementary Metal-oxide-semiconductor DevicesComplementary Metal-oxide-semiconductor ScalingMagnetoresistive Random-access MemoryMemory Circuit DesignSoft ErrorsStatic Power DissipationStatic Power Reduction
Following the scale down of complementary metal-oxide semiconductor (CMOS) technology, radiation-induced soft errors have become a concerning issue in CMOS circuit design. Today's integrated circuits suffer from single event double node upset (SEDU) that takes place when an energetic particle strike affects two adjacent nodes. In this letter, a magnetic random access memory block capable of tolerating SEDUs is proposed and evaluated. The proposed circuit utilizes a hybrid design of magnetic and CMOS-based technology that considerably reduces the static power, improves the performance, and offers the advantage of nonvolatility. Simulation results validated that the proposed circuit is fully single event upset and also SEDU immune beside the other advantages offered.
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