ESD Robust Fully Salicided 5-V Integrated Power MOSFET in Submicron CMOS

Abstract

A novel high electrostatic discharge (ESD), robust fully salicided 5-V integrated CMOS power MOSFET design is developed and demonstrated without the use of conventional salicide blocking ballast resistor. This scheme builds the ballast resistors on the top of the source and drain, without any increase in silicon footprint unlike prior methods, while maintaining standard transistor parametric performance.